Crest Factor Reduction - LLCFR01

Crest factor reduction is a key component in modern digital amplifier and linearization systems. Using active control of transmit signal error vector magnitude (EVM), Crest Factor Reduction can significantly reduce waveform peak to average power ratio (PAPR), while maintaining spectral purity and improving amplifier linearity, efficiency and cost.


The Affarii LLCFR01 processor is an advanced non-linear cancellation engine that offers low implementation resource and power consumption. The CFR processor is modulation agnostic, supporting single and multi-carrier configurations, and can self training without knowledge of system configuration.

The LLCFR01 core is designed support peak reduction down to 6dB PAPR dependent on modulation scheme and been qualified for operation with 3GPP WCDMA and LTE standards and with DVB-T/T2 and DAB Broadcast Standards.


  • Multi-stage Peak Cancellation.
  • Reduction to 6.0dB PAPR.
  • Input Modulation Agnostic.
  • MCPA Waveform Support.
  • Self Training Algorithm (optional).
  • Typical Performance:
    • WCDMA: 6.5dB PAPR @ 6% EVM.
    • LTE : 7.0dB PAPR @ 4% EVM.
    • DVB-T2: 8.5dB PAPR @ -35dB MER.
  • ACP1 >70dBc @ 6.0db PAPR Output.

Block Diagram

CFR Block Diagram

Figure 1: LLCFR01 - Low Latency CFR Block Diagram.


The LLCFR01 Crest Factor Reduction processor consists of up to four cascaded peak reduction stages with an input pre-scaling and output post-scaling gain element. The number of stages and resource of each peak reduction stage are configured for the target application and IP block creation time based on the peak reduction level and maximum number of carriers that must be supported.

CFR Reduction CFR Reduction

Figure 2: CFR Peak Reduction.


The LLCFR01 processor is available as a standalone IP block for Altera and Lattice FPGAs or as part of the digitalTRX solution set.

For further information please contact